On the Performance of Bus Interconnection for SOCs

The choice and design of communication architecture are critical for SOC design. The communication architecture may heavily influence the overall performance, and also determines the salability of the whole system. Among several communication architectures proposed for SOCs, shared-bus has been widely used. Some doubts are cast on this approach today, as it is likely to be the bottleneck for the current and future SOCs. In this paper, we use analytical model based simulator and abstracted traces of image processing applications to simulate the Global Bus architecture of Cradle’s Universal Micro System (UMS). Our simulation shows that (i) with carefully designed protocols, shared-bus is efficient enough for current and future high performance SOCs; (ii) instead of the shared-bus, the SDRAM is more likely to be the bottleneck, especially for streaming applications. For the applications in our experiments, the SDRAM gets saturated as early as 30% of the Global Bus utilization. We also explore the relationship between the depth of buffers and the performance of the Global Bus in our work.